There are sixteen data output and sixteen data input lines. The logic sense of these lines is user configurable. A DOUT Clear jumper is provided that will set all ouput data lines low after a reset or power up.

The three handshake lines are the Peripheral Control line (PCTL), Peripheral Flag line (PFLG), and Input/Output line (IO). The Peripheral control line is set by the computer to initiate a data transfer. The peripheral uses the Peripheral Flag line to acknowledge a transfer. The logic sense of these two lines are user configurable. The Input/Output line indicates the direction of data flow to the peripheral. A high signal indicates an input from the peripheral while a low signal indicates an output to the peripheral.

The special purpose lines are External Interrupt Request (EIR), Peripheral Status (PSTS), and Peripheral Reset (PRESET). The External Interrupt Request line allows the peripheral to interrupt the computer. The Peripheral Status line can be used to indicate the current status of the peripheral. The logic sense of this line is user configurable. The Peripheral Reset line pulses low for a least 15 microseconds to reset the peripheral when the computer I/O reset takes place.

The general purpose lines are two control lines, CTL0 and CTL1 that the computer can set and two status lines, STI0, and STI1 that the computer can read.

The signal drive requirements are 2 mA low on the data lines, 4.5 mA on the signal lines (PFLG, PSTS, STI0, STI1). The maximum voltage allowed is 5.5V. A high value is greater- than 2.0V and a low value is less-than 0.7V on the data lines and less-than 0.6V on the signal lines.

Driver Circuit Illustration Here Peripheral Signal Receiver Requirements The GPIO interface outputs are all driven with open collector gates. This means that the line is either left floating free for a high signal or is pulled to ground for a low signal. This causes two effects; first the computer can write to devices requiring any voltage up to 30V, and second, the driver must be pulled up to the high voltage or the peripheral will read a low value.

The HND switch on the interface selects one of two handshake modes to synchronize data transfers: Full-Mode or Pulse Mode. If the peripheral uses pulses to handshake data transfers and meets the timing requirements, the Pulse-Mode Handshake may be used. The Full-Mode Handshake should be used if the peripheral does not meet the Pulse Mode timing requirements.

The computer reads the contents of the data buffers on the GPIO interface and not the actual input lines. The switch selected data-clock type determines when the data is loaded into the data buffers. A RDY clock loads the data buffers on a busy-to-ready transition of PFLG. A BSY clock loads the data buffers on a ready-to-busy transition of PFLG. The RD clock loads the data buffers as it is reading the buffers.

A BSY or RDY clock would normally be chosen if HTBasic OUTPUT and ENTER statements are to be used with the GPIO interface. These statements require a complete handshake during which the data will be lached. The latch time should be set, with the BSY and RDY clock, to a time when the peripheral has valid data on the data lines.

If STATUS statements are used to read the data buffers, then the clock would normally be set to RD so that the line data will be clocked in. If the clock source is BSY or RDY and FPLG is not toggled the STATUS statement will always return the same value regardless of the input lines because the buffers are never loaded with new data.

A complete handshake involves five steps.

Step 1. The computer performs a peripheral status check by reading the PSTS line before the start of an OUTPUT or ENTER statement. If it is a logical 1 the computer continues with the transfer.

Step 2. The computer performs a peripheral ready check by reading the state of the PFLG line before proceeding with the transfer of each data word. If PFLG is in the ready state the computer proceeds, if not, the computer waits until the peripheral puts PFLG in the ready state. If the state of the PFLG is changed it is a Full-Mode handshake, otherwise it is a Pulse-Mode handshake.

Step 3. The computer initiates the transfer by setting the PCTL and IO lines. The IO line indicates the direction of the data transfer while PCTL indicates the start of a transfer.

Step 4. The peripheral must read the date lines during an OUTPUT or write the data onto the data lines during an INPUT statement.

Step 5. The peripheral acknowledges that it has read or written the data by setting or clearing the PFLG line.

Because the GPIO interface can support many modes of handshaking the data between the computer and peripheral devices, some study of the device is required to determine the best method. The GPIO manual shows detailed timing diagrams for nine handshaking modes.

When a timeout takes place the interface is reset. This involves the PCTL line being set then cleared and PRESET is pulsed low. If the error is not trapped with an ON TIMEOUT statement, the program terminates with a timeout error.

Interface Ready Interrupt
When the interface ready bit is set, an interrupt will occur whenever the interface becomes ready. In Full-Mode handshake the interface is ready whenever PCTL is clear and PFLG is ready. In Pulse-Mode handshake the interface is ready when PCTL is clear regardless of the state of PFLG.

External Interrupt Request
When the External Interrupt Request (EIR) bit is set, an interrupt will occur whenever the EIR line goes low. The polarity of this line cannot be changed. This line muse be kept low until it is inside the service routine or it may be missed by the program.