Support: GPIO Theory of Operation

Referenzen

Schulungsmaterial 

 Hauptseite Support

GPIO-Support 

This document applies to all TAMS GPIO interfaces. 

Data Lines

The data lines of the TAMS GPIO interface consist of the lines designated for data input, DI0 through DI15, and those for data output, DO0 through DO15. Like all the TAMS GPIO lines, the default logic sense (polarity) of the data lines is low true. However, you can change the polarity of either set of data lines to high true with the TAMS GPIO card polarity in SICL configuration or in your SICL software. E.g. SICL C call igpioctrl (id, I_GPIO_POLARITY,<val>).

You can configure the TAMS GPIO card data lines in either of the following two ways:

Note 

When using bi-directional mode, make sure the peripheral controlled by the TAMS GPIO card is bi-di compatible. If bi-di mode is selected and the peripheral is not bi-di compatible the TAMS GPIO card or peripheral's output buffers may be damaged.

Given the two different configurations that are possible, this section discusses the data lines for the TAMS GPIO card with regard to each particular configuration you can use. The first subsection explains how the data lines function in Compatibility Mode, and the second explains how they function in Enhanced Mode. The final subsection then describes the choices available for data-in-clocking.

Compatibility Mode

When configured in Compatibility Mode, all the lines of the TAMS GPIO card appear the same as the HP 98622 GPIO interface.

This is summarized in the following figure.

Overview of Compatibility Mode

Thus, in Compatibility Mode, data input and data output are handled on separate, independent ports. Each port (the data input port and the data output port) has 16 lines (labeled 0 through 15) for a maximum of 16 bits each. You can configure the logic level of either port as either high-true or low-true.

If you are using a TAMS GPIO card with the same peripheral device and same cable as an existing HP 98622 application, you should use Compatibility Mode. If your existing HP 98622 application uses an 8 bit data width, note that the upper data byte is undefined on the TAMS GPIO card. Although every effort was made to provide complete compatibility, there is no guarantee that the undefined lines on the TAMS GPIO card and the undefined lines on the HP 98622 will assume matching states at all times. This, however, will not represent any incompatibility or other problems. If both the GPIO interface and the peripheral device use the same 8-bit width, the other 8 bits cannot be controlled or examined by either the TAMS GPIO card or peripheral device. This assures that the state of the other 8 bits have no effect at all. In a properly designed application the GPIO interface and the peripheral device will always be configured with the same data widths.

The next subsections describe the data input and the data output lines Compatibility Mode.

Data Input Lines

In Compatibiliy Mode, there are 16 data input lines labeled DI0 through DI15. Input lines DI0 through DI7 are the low (least-significant) byte, and DI8 through DI15 are the high (most-significant) byte. Three choices of data-in clocking are available for each byte or for the 16 bit word. Refer to the "Data-In Clocking" subsection later in this section for more information.

The data input lines are TTL lines. A resistive divider biases open lines to approximately +3.4 volts. The following figure shows one data input line and some possible ways a peripheral device might connect to it.

Caution The voltage applied to a data input line must never exceed + 5.5 volts.

Electrical Detail of Data Input Lines

The following is a list of requirements for the data input lines. Any peripheral driver circuit must be compatible with these input requirements:

Iinlow max = -2.3 ma (Vinlow = 0.4 V)

Vinmax = 5.5 V

Vinhigh > 2 V

Vinlow < 0.7 V

Data Output Lines

In Compatibility Mode, there are 16 data output lines labeled DO0 through DO15. Output lines DO0 through DO7 are the low (least-significant) byte, and DO8 through DO15 are the high (most-significant) byte.

The data output lines are open-collector drivers which can sink a maximum current of 40 ma. For best flexibility, no internal pull-ups are used. Thus, the peripheral device must provide a pull-up to a positive voltage, not to exceed 30 volts. The following figure shows one data output line and some possible ways a peripheral device might connect to it.

CAUTION Do not apply a negative voltage to the data output lines.

Electrical Detail of Data Output Lines

The following is a list of requirements for the data output lines. Any peripheral receiver circuit must be compatible with these output requirements:

VoutLow

(IoutLow = 16 ma) = 0.4 V max

(IoutLow = 40 ma) = 0.7 V max

VoutHigh (open collector) = 30 V max

Ioutlow = 40 ma max

Iouthigh(Vout = 30 V) = 250 ua

Enhanced Mode

When configured in Enhanced Mode, the TAMS GPIO card uses a bi-directional data port on the lines normally designated for data input (DI0 through DI15). The data output lines (DO0 through DO15) are thus free to be used as independent auxiliary control lines. This is summarized in the following figure:

Overview of Enhanced Mode

Enhanced Mode allows more interfacing flexibility than Compatibility Mode. However, Enhanced Mode is only appropriate for use with peripheral devices that have bi-directional data ports.

The next subsections describe the bi-directional data lines and the auxiliary control lines in Enhanced Mode.

Bi-Directional Data Lines

In Enhanced Mode, the bi-directional data port is TTL level. It has resistive pull-ups up to + 5 volts. The peripheral device must use a data port compatible with bi-directional protocol.

The TAMS GPIO card port direction is controlled by the I/O (Input/Output) direction control line. Likewise, the peripheral device must use the I/O line to set the proper direction of its data port. The I/O line is low when the TAMS GPIO card drivers are enabled (output) and is high when the TAMS GPIO card drivers are disabled (input). The following figure shows one bi-directional data line and one way a peripheral device might connect to it.

Caution The voltage applied to the bi-directional data lines (DI0 through DI15) must never exceed + 5.5 volts.

Electrical Detail of Bi-Directional Data Lines

Caution When connected to a TAMS GPIO card in Enhanced Mode, the peripheral device must never attempt to drive the data lines at the same time that the TAMS GPIO card drivers are enabled. Also, the peripheral device must not exceed TTL voltage or current levels on the data lines.

Failure to follow these specifications can result in damage to the TAMS GPIO card hardware interface or peripheral device. If your peripheral device cannot conform to these specifications, do not use Enhanced Mode. See the previous subsection on "Compatibility Mode" instead.

Auxiliary Control Lines

The auxiliary control lines created by Enhanced Mode are connected to the 7406 open-collector drivers described in the previous "Compatibility Mode" subsection. They have the same 30 volt, 40 ma limits. Like the control output lines (CTL0 and CTL1), the auxiliary control lines are write-only and use no handshake with the peripheral device.

NOTE The auxiliary control lines created by Enhanced Mode inherit the same logical polarity configured for the data output port.

Programming Notes. In C programs, the auxiliary control lines are set by the I_GPI0_AUX parameter of the igpioctrl function in HP SICL. For example:

igpioctrl (id , I _ GPI 0 _AUX , value);

For more information, please refer to the HP SICL documentation.

In HP BASIC/UX 700 programs, the auxiliary control lines are set by CONTROL register 4. For more information, please refer to the HP BASIC/UX 700 documentation.

Data-In Clocking

Three choices of data-in clocking are available for each byte or for the 16-bit word. You set this in the TAMS GPIO card read_clk or Read Clock configuration value in your software.

As explained earlier, the 16 data input lines are divided into two data bytes. The lower, least-significant byte consists of data input lines DI0 through DI7. The upper, most-significant byte consists of data input lines DI8 through DI15. Data-in clocking can be selected from any of three clock sources for both upper and lower bytes.

The following figure shows the timing diagram for data-in clocks on a full standard read. The clocking for the other operating modes, including pulse mode, follows these same guidelines.

Data-In Clocking Timing Diagram

The next subsections describe the three clocks which can be selected to latch data. The descriptions are applicable to either the upper or lower byte.

Read Clock

The Read clock causes the data to be latched into the data input register when the register is read. (See the previous figure, phase 1.) The Read clock accomplishes this by clocking the register on the leading edge of the read strobe of the register. During a DMA transfer, the Read clock causes the data to be latched with DMA acknowledge which is generated by the DMA controller.

Bsy Clock

The Busy clock latches the data into the data input register by the leading edge of the PFLG line. (Refer to the previous figure, phase 2.) This transition also clears the PCTL line. This is the ready-to-busy transition of the PFLG line.

Rdy Clock

The Ready clock latches the data into the data input register by the trailing edge of the PFLG line. (Refer to the previous figure, phase 3.) This is the busy-to-ready transition of the PFLG line.

Peripheral Information Lines

Ten lines control the exchange of information between the TAMS GPIO card GPIO interface and the peripheral device. Five of these lines are outbound to control the peripheral:

The other five peripheral information lines are inbound to communicate the state of the peripheral:

All 5 incoming lines have Schmitt trigger receiver circuits. These circuits accept signals with slow rise and fall times. They also provide good noise immunity. Although the voltage on these lines must not exceed 5.5 volts, there are no restrictions on the input rise and fall times.

All of the peripheral information lines are described in the following subsections.

Peripheral Control and Peripheral Flag Handshake Lines (PCTL and PFLG)

The peripheral control line (PCTL) and the peripheral flag line (PFLG) are used as a 2-wire handshake between the TAMS GPIO card interface and the peripheral device. The TAMS GPIO card interface controls the PCTL line, and the peripheral device controls the PFLG line.

The TAMS GPIO card provides both handshake modes of the HP 98622, plus an additional async output mode. Also, the logic sense of the PCTL and PFLG lines on the TAMS GPIO card can be configured differently. Like all the TAMS GPIO card lines, PCTL and PFLG have the default logic sense (polarity) of low-true. The polarity of either or both the PCTL and PFLG lines can be changed with the TAMS GPIO card polarity configuration value in your software.

If you are porting an HP 98622 application, notice that the bits in the polarity field correspond to DIP switches on the HP 98622 interface card. However, many old cards had " 1" and "0" markings that were backwards from the electrical state of the switch. When transferring your old settings to the polarity value, keep in mind that all the bits might be upside-down (0® 1).

The following subsections describe each handshake line (PCTL and PFLG), as well as the handshake modes for the TAMS GPIO card.

PCTL Line

The PCTL line is an outgoing line to the peripheral. PCTL has two states: set and clear. The TAMS GPIO card sets the PCTL line to start a handshake.

The peripheral device clears the PCTL line when a ready-to-busy transition occurs on the PFLG line. (A ready-to-busy transition is when PFLG goes from the ready state to a busy state.) During an output transfer, PCTL is delayed to allow new output data to settle. This delay is explained in the next subsection, "PCTL Delay."

PCTL Delay. You can select the delay (settling time) from when data is placed on the GPIO bus to when PCTL is Set during an output data transfer. The delay selection is set with the TAMS GPIO card configuration (SICL ioconfig) or it can be changed from within the software with igpioctrl (id,I_GPIO_PCTL_DELAY, <val>). Accepted values are HP 2074/5 compatible. In addition, a direct value in nanoseconds could be specified. Acceptable values in nanoseconds are between 90 and 245,000 inclusive (90 nanoseconds to 245 microseconds). The delay selections are: 200 ns, 400 ns, 700 ns, 1.2µs, 2 µs, 5 µs, 10 µs, and 50 µs.

PFLG Line. The PFLG line is an incoming line from the peripheral device. PFLG must be driven to complete a data transfer. PFLG has two states: ready and busy.

When the peripheral device is ready to transfer data, it responds by setting PFLG to ready. When the computer sets PCTL, the computer has initiated a data transfer either in or out, depending on the state of the I/O line. (See the "Input/Output Direction Control Line (I/O)" later in this section.)

After the data transfer occurs, the peripheral device responds by setting PFLG to busy. This causes the TAMS GPIO card to clear the PCTL line on the ready-to-busy transition. In the full handshake mode, the interface waits until the peripheral device makes PFLG ready before initiating another data transfer. In the pulse handshake mode, the interface initiates the transfer without waiting. Refer to the next subsection on "Handshake Modes" for more information.

Handshake Modes. Like the HP 98622, the PCTL and PFLG lines on the TAMS GPIO card can be used for full-mode or pulse-mode handshakes. Additionally, the TAMS GPIO card provides an async-mode for output.

You set the handshake modes with the TAMS GPIO card mode or Handshake configuration value in your software. All of the handshake modes for the TAMS GPIO card are explained in the following subsections.

Full-Mode Handshakes. With full-mode handshakes, the computer first checks to see that the peripheral device is Ready before initiating the transfer of each byte or word. With this handshake mode, the interface detects Ready when both PCTL is Clear and PFLG is Ready. If the peripheral device does not indicate Ready, the computer waits until a Ready is indicated.

During a write cycle, when a Ready is sensed, the computer drives the I/O line Low, then places data on the appropriate data lines. The interface then waits the PCTL delay time before initiating the transfer by placing PCTL in the Set state.

The peripheral acknowledges the computer's request by placing the PFLG line Busy; this PFLG transition automatically Clears the PCTL line. However, the computer cannot initiate further transfers until the peripheral is Ready with full-mode handshake. Ready is not sensed until both PCTL is Clear and PFLG is Ready.

The data on the data lines is held valid from the time PCTL is Set until after the peripheral device indicates Ready. The peripheral may read the data any time within this time period.

The following two figures show the order of events during full-mode output and input operations.

Full Mode Timing Diagram:

Output Operation

Full-Mode Timing Diagram:

Input Operation

Pulse-Mode Handshakes. The main difference between full-mode and pulse-mode handshake is that the PFLG line is not checked for Ready before the computer initiates pulse-mode handshakes. With pulse-mode handshakes, the computer may initiate a subsequent data transfer as soon as the PCTL line is Cleared by the Ready-to-Busy transition of PFLG.

This absence of the PFLG check can give a slightly higher data-transfer rate than possible with full-mode handshakes. However, in some cases, it places additional timing restrictions on the peripheral device's response time.

During a write cycle, the PFLG line is not checked for Ready before the computer drives the I/O line Low and places data on the appropriate data lines. A PCTL delay time later, the interface initiates the transfer by placing PCTL in the Set state.

The peripheral device acknowledges by placing PFLG Busy; this transition automatically Clears PCTL. Then the computer may initiate another transfer any time after PCTL is Clear, possibly before the peripheral places PFLG in the Ready state.

The following two figures show the order of events during pulse-mode output and input operations.

Pulse-Mode Timing Diagram:

Output Operation

Pulse-Mode Timing Diagram:

Input Operation

Async Output Mode. The TAMS GPIO card async output mode is not really a handshake, because it completely ignores the PFLG line, and it has no concept of peripheral Ready. It is intended for peripheral devices which cannot implement a handshake, but need only a fleeting strobe to catch their data. The following figure shows the order of events in async output mode.

Async Output Mode Timing Diagram

The computer drives the I/O line low (not shown) and places data on the data out lines (t0). Soon after, the interface puts the PCTL line in the Set state (t1). The interface then waits the specified PCTL delay time, and clears the PCTL line (t2). In other words, there is a PCTL pulse immediately after each data output.

The width of the PCTL pulse is configurable by the PCTL delay configuration value in your software. The time from t0 ® t1 depends upon other handshake parameters. In auto-handshake mode, it is very short (around 50 ns). In standard-handshake mode, this time is roughly 500 ns. Because t0 ® t1 is short and not controllable, it is recommended that the peripheral device latch its data at the trailing edge (t2) of PCTL, rather than the leading edge.

Standard-Handshake and Auto-Handshake Modes. Please note that this discussion does not refer to the type of handshake configured; it refers only to the method for starting that handshake. The handshake types (full and pulse) are discussed earlier in this section.

The term "standard" handshake is not especially descriptive; it refers to the polling method used by the old HP 98622 drivers. In standard-handshake mode, the computer starts a handshake by writing to a PCTL register on the interface. The driver may perform this operation for you, as with an OUTPUT statement in HP BASIC/UX 700, or an iread function in HP SICL. Or you may perform this operation explicitly, as with CONTROL or igpioctrl.

Auto-handshake mode is the default method for the TAMS GPIO card, and is the only method used for DMA transfers. In this mode, the computer starts a handshake simply by accessing the data register on the interface. The separate step of writing to a PCTL register is avoided, so performance is increased.

The operation that benefits the most from auto-handshake mode is an inbound transfer of known size. Examples are ENTER 12 USING " 1024A", or iread with no itermchr. With a sufficiently fast peripheral device, auto-handshake mode can be 10% to 2096 faster than standard-handshake mode.

Auto-Handshake can always be used for outbound operations like OUTPUT or iwrite. Keep in mind that the most significant factor in outbound performance is the amount of PCTL delay time. However, you should not reduce the PCTL delay to the point where data integrity is lost. The PCTL delay time should be set according to the characteristics of your GPIO cable and peripheral device.

Programming Notes

Auto-handshake mode is obviously incompatible with programs that implement a custom, explicit handshake. Attempts to manually set PCTL (with I_GPIO_SET_PCTL in HP SICL, or with HP BASIC/UX 700 register 1) during auto-handshake mode will cause a program error. Therefore programs that implement an explicit handshake must disable auto-handshake mode.

Auto-handshake mode is the default for the TAMS GPIO card. In C programs, it can be disarmed by the I_GPIO_AUTO_HDSK parameter in HP SICL.

For example:

igpioctrl(id, I_GPIO_AUTO_HDSK, 0);

The current auto-handshake state is reported in the I_GPIO_INFO value.

For example:

int value;

igpiostat(id, I_GPIO_INFO, &value);

if (value & I_GPIO_AUTO_HDSK)

printf("Auto-Handshake enabled\n");

For more information, please refer to the HP SICL documentation.

In HP BASIC/UX 700 programs, auto-handshake mode is controlled and reported in register 6. For more information, please refer to the HP BASIC/UX 700 documentation.

Input/Output Direction Control Line (I/O)

The input/output direction control line (I/O) is an outbound line to the peripheral device. I/O indicates to the peripheral which direction the data transfer is to go. I/O goes high when the TAMS GPIO card GPIO interface is reading data and low when the interface is writing data.

Peripheral Status Line (PSTS)

The peripheral status line (PSTS) is an incoming line from the peripheral device. It signals to the computer that all is "OK" with the peripheral. PSTS has two states: not OK and OK.

The logic sense (polarity) for PSTS can be changed from low-true (the default) to high-true through the TAMS GPIO card polarity configuration value in your software.

Peripheral Reset Line (P_RESET)

Note This is the same as the PRESET line on the HP 98622 GPIO interface.

The peripheral reset line (P_RESET) is an outbound line to the peripheral device. P_RESET is used to reset and/or initialize the peripheral device. P_RESET is pulsed low when the computer is first turned on. It is also pulsed low when the interface is reset by iclear in HP SICL, or by Control register 0 in HP BASIC/UX 700. This pulse lasts for at least 15 m s.

External Interrupt Request Line (EIR)

The external interrupt request line (EIR) is an inbound line from the peripheral device. You can use EIR to trigger an interrupt on an external event. EIR should be held low until the interrupt service routine has been invoked and has acknowledged the interrupt. The method for acknowledging an EIR interrupt is device-dependent. Please consult your peripheral's hardware documentation.

Control Output Lines (CTL0 and CTL1)

The control output lines (CTL0 and CTL1) provide two additional, outgoing control lines to the peripheral device. You can use these low-true logic signals for any purpose to control the peripheral.

CTL0 and CTL1 have two states: control set (low) and control clear (high). These lines are latched and can be set or cleared (low = 1, high = 0) by a control operation. The states of these lines are cleared at power up and are unchanged after a reset.

Status Input Lines (STI0 and STI1)

The status input lines (STI0 and STII) provide two additional, incoming status lines from the peripheral device. You can use these low-true logic signals for any purpose that resets the status of the peripheral.

STI0 and STI1 have two states: low (logic 1) and high (logic 0), and they cannot be inverted. You can examine the state of these lines with a status operation.

Direct Memory Access (DMA)

Direct Memory Access (DMA) provides high transfer performance and uses fewer computer resources, thus increasing overall system performance. DMA transfers can be done using either byte (8 bit) or word (16 bit) accesses. This data width is set by the igpiosetwidth function in HP SICL for HP-UX, or the ASSIGN statement in HP BASIC/UX 700.

Your program might make requests that are inconsistent with DMA. One example is character matching on inbound data. The DMA works strictly by counting; it cannot detect other termination reasons such as line feed characters. If you specify itermchr or I_GPIO_READ_EOI or use free field ENTER in HP BASIC/UX 700, the computer will not use DMA. The TAMS driver will use interrupt driven transfer just for that request. Of course, DMA is not used if you explicitly disable it, as with the HP SICL function: ihint(id,I_HINT_USEPOLL)